1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to read architectures for non-volatile memories.
2. Related Art
Non-volatile semiconductor memories and arrays are widely used to store written or programmed information or data. The information or data, represented as a “1” or “0”, is stored in individual memory cells, such as EEPROMs, EPROMs, NOR-type flash memory cells, or NAND cells. An array of such individual memory cells are interconnected by columns of bit lines and rows of word lines. Associated bit-line and word-line decoders allow specific memory cells to be accessed or read, erased, and programmed by applying appropriate voltages to selected bit lines and word lines. In a typical read operation, a read circuit senses the threshold voltage of a floating gate transistor in a memory cell to determine the value or data stored in the cell. The sensing can be with a conventional sense amplifier that compares the voltage or corresponding current from the memory cell with a reference voltage or current. This comparison, as is known in the art, allows the content stored in the accessed memory cell to be read out.
FIG. 1 shows portions of a conventional memory array 100, which includes N sectors 102, with each sector partitioned into M groups 113 of L memory cells in a row. Each column of groups 113 shares a global bit line 104, a reference global bit line 106, a bit line multiplexer 108, a dummy bit line multiplexer 110, and a sense amplifier 112. Within each sector, there are M*L sub-bit lines 114 and M reference sub-bit lines 107. Many elements are not shown for clarity, such as memory cells within each sector 102, word lines along the x-direction, and word line and bit line decoders. Note also that dummy bit line multiplexers 110 are typically located away from bit line multiplexers 108, as will be discussed below. Within each sector, memory cells are arranged in rows and columns, with each group 113 of L memory cells along a row having L global bit lines 104 and one reference global bit line 106.
For example, for an array having K=4096 memory cells across and the memory cells within each sector partitioned in groups of L=512 memory cells, there are M=K/L=8 reference global bit lines 106. Each partitioned group 113 within a sector is also associated with one bit line multiplexer 108, one dummy bit line multiplexer 110, and one sense amplifier 112. The bit-line multiplexers are L:1 multiplexers, and the dummy bit line multiplexers are similar in structure to the bit line multiplexers, as will be discussed below. The output signal from the bit line multiplexer (representing the value stored in the selected memory cell) and the output signal from the dummy bit line multiplexer (representing a reference signal) are input to the sense amplifier. The sense amplifier compares the two input signals and generates a signal representing the data stored in the selected memory cell.
Each row of memory cells in a sector 102 is associated with one word line. Each column of memory cells in a sector 102 is associated with one sub-bit line 114 that spans only the height of the sector, where the sub-bit line is connected to a source (or drain) of each memory cell in the column. One global bit line 104 that spans the entire height of the N sectors 102 is coupled to each of the N sub-bit lines 114 along a column in the array by a switch or select transistor (not shown). When a desired memory cell is to be read, the appropriate voltages are applied to a corresponding word line and select line, which charges or discharges the attached sub-bit line depending on the type of memory cell and data stored in the cell. The sub-bit line associated with the selected memory cell is electrically coupled to its corresponding global bit line via the switch or select transistor. This global bit line is then selected by the L:1 bit line multiplexer for use by the sense amplifier. During the read operation, only one sector is being selected at a time. Sub-bit lines in unselected sectors are electrically isolated from the main bit line with their select transistors being turned off. Such an arrangement and scheme is known and is commonly referred to as a divided bit line scheme or architecture.
Divided bit line schemes are used to improve read performance or reduce read times, which can become increasingly long with ever-increasing array sizes. During a read operation, the selected bit-line is charged or discharged by the cell current to a pre-defined level, as is known in the art. The time needed to charge or discharge is proportional to the total parasitic capacitance associated with the bit-line. Thus, as memory arrays become larger, the bit-lines become longer and the bit line multiplexers become wider, resulting in larger parasitic capacitances. This in turn increases signal development time.
The value of the total capacitance that is to be charged or discharged by cell current during a read operation can be expressed as follows:Ctotal=CDL+CBLM+CGBL+CSBL  (1)where Ctotal is the total capacitance, CDL is the data line capacitance, CBLM is the bit line multiplexer capacitance, CGBL is the global bit line capacitance, and CSBL is the sub-bit line capacitance. Both CDL and CBLM are proportional to the width of the bit line multiplexer. CSBL is linearly proportional to the length of the sub-bit line or the number of cells on the sub-bit line. Thus, by dividing the bit lines into smaller sub-bit lines, the total bit-line capacitance is reduced and read times are improved. The signal development time for a read operation can be given as follows:                               t                      SD            ,            total                          =                                                                              C                  total                                ·                Δ                            ⁢                                                          ⁢              V                                      I              cell                                =                                                                                                                C                      DL                                        ·                    Δ                                    ⁢                                                                          ⁢                  V                                                  I                  cell                                            +                                                                                          C                      BLM                                        ·                    Δ                                    ⁢                                                                          ⁢                  V                                                  I                  cell                                            +                                                                                          C                      GBL                                        ·                    Δ                                    ⁢                                                                          ⁢                  V                                                  I                  cell                                            +                                                                                          C                      SBL                                        ·                    Δ                                    ⁢                                                                          ⁢                  V                                                  I                  cell                                                      =                                          t                                  SD                  ,                  DL                                            +                              t                                  SD                  ,                  BLM                                            +                              t                                  SD                  ,                  GBL                                            +                              t                                  SD                  ,                  SBL                  ,                                                                                        (        2        )            where ΔV is the change of signal level needed to be developed for the sense amplifier to produce a correct output corresponding to stored data in the selected memory cell, Icell is the cell current, tSD,DL is the time it takes Icell to develop ΔV on the data line, tSD,BLM is the time it takes Icell to develop ΔV on the capacitance associated with the bit line multiplexer, tSD,GBL is the time it takes Icell to develop ΔV on the global bit line, and tSD,SBL is the time it takes Icell to develop ΔV on the sub-bit line. As CSBL decreases, Ctotal decreases (see equation (1)), which decreases the total signal development time tSD,total (see equation (2)).
However, as the minimal feature size of the semiconductor manufacturing process continues to shrink, dimensions of the memory cell become smaller, memory of higher density becomes achievable and desirable. Higher density results in larger array size and in turn larger parasitic capacitances. At the same time, smaller memory cells usually result in smaller cell currents to charge or discharge such capacitances. Both larger capacitance and smaller cell current contribute to the increase of the sense time.
Another disadvantage with such a divided bit line scheme is that of a mismatch in capacitance loading between a regular bit line and a reference bit line. In order to accurately sense the value in a selected memory cell, the capacitance associated with the dummy bit line multiplexer (element 110 in FIG. 1) should be as closely matched to the capacitance of the bit line multiplexer (element 108 in FIG. 1) carrying the signal from the selected memory cell as possible. To that objective, the dummy bit line multiplexer will have a similar structure as the bit line multiplexer. For example, if the bit line multiplexer is a 16:1 MUX, the bit line multiplexer is formed with 16 transistors, each having one terminal connected to a global bit line, one terminal commonly connected together as the MUX output, and the gate coupled to a select signal for selecting the desired bit line for the output. The dummy bit line multiplexer would then also have 16 transistors, with one transistor connected to the reference bit line and the remaining 15 transistors turned off. This structure then has a similar capacitance to the regular bit line multiplexer.
However, because of space restrictions, dummy bit line multiplexer 110 cannot be placed adjacent or near bit line multiplexer 108 as shown in FIG. 1. In a practical layout, the dummy bit line multiplexer is located along a periphery of the array. As such, signals traveling through the dummy bit line multiplexer must propagate through longer transmission lines to reach the sense amplifier. Consequently, the mismatch of capacitance loading between the dummy bit line multiplexer and the regular bit line multiplexer is increased. This mismatch reduces the read performance of the array by increasing read time to maintain the same level of accuracy. Building a reference bit line and reference bit line multiplexer with identical layout and parasitic capacitances to those of a regular bit line and bit line multiplexer is very costly and/or greatly increases the array size to the extent that such an option is not practical.
Accordingly, there is a need for an improved read architecture and method for nonvolatile memory arrays that overcomes the disadvantages of conventional read architectures, such as described above.